[K-1] 3D Integration and Stress Optimization

2:30 PM - 2:45 PM JST(5:30 AM - 5:45 AM UTC)

[K-1-05] Investigation of Thermal Warpage of Thinned Foundry Chips in Multichip to Wafer 3D Integration

〇Sota Koyama¹, Yuki Sakamoto¹, Hiroki Nakamura¹, Takafumi Fukushima^1,2, Tetsu Tanaka^1,2 (1. Department of Mechanical Systems Engineering, Graduate School of Engineering, Tohoku Univ. (Japan), 2. Department of Biomedical Engineering, Graduate School of Biomedical Engineering, Tohoku Univ. (Japan))