Session Details
[K-1]3D Integration and Stress Optimization
Tue. Sep 15, 2026 1:15 PM - 2:45 PM JST
Tue. Sep 15, 2026 4:15 AM - 5:45 AM UTC
Tue. Sep 15, 2026 4:15 AM - 5:45 AM UTC
Room K(108, 1st Floor)
Session Chair:Katsuhiko Suzuki(Samsung Japan Corp.), Daisuke Ikeno(KIOXIA Corp.)
[K-1-01 (Invited)]Perspectives of CoSn kagome metal as anisotropic conductor for advanced interconnects
〇Tomoya Nakatani1 (1. NIMS (Japan))
[K-1-02]Investigation of Laser-Induced Crack Deflection in Through-Glass Vias
〇Wei Feng1, Yusuke Takei1, Takeshi Kobayashi1 (1. Natl. Inst. Adv. Indus. Sci. & Tech. (Japan))
[K-1-03]Development of a Stress Suppression Liner Formed from a Negative Thermal Expansion Material for Through-Silicon Via (TSV) Applications
〇Yiqing Xu1, Ruobo Lan1, Hisashi Kino1 (1. Kyushu Univ. (Japan))
[K-1-04]Development of the Underfill with Negative Thermal Expansion Materials to Suppress Local Thermal Stress in 3D ICs
〇RUOBO LAN1, Yiqing Xu1, Hisashi Kino1 (1. Kyushu Univ. (Japan))
[K-1-05]Investigation of Thermal Warpage of Thinned Foundry Chips in Multichip to Wafer 3D Integration
〇Sota Koyama1, Yuki Sakamoto1, Hiroki Nakamura1, Takafumi Fukushima1,2, Tetsu Tanaka1,2 (1. Department of Mechanical Systems Engineering, Graduate School of Engineering, Tohoku Univ. (Japan), 2. Department of Biomedical Engineering, Graduate School of Biomedical Engineering, Tohoku Univ. (Japan))
