Presentation Information
[PS-12-05]A Fast-Locking, Low-Power, and Low-Jitter Sub-Sampling PLL with a Dead Zone Automatic Controller in 16nm FinFET
〇Jyun-Si Lin1, Yu-Lung Lo1, Wei-Bin Yang2 (1. The Univ. of National Kaohsiung Normal (Taiwan), 2. The Univ. of Tamkang (Taiwan))