[15a-M_124-1~13] 13.5 デバイス／配線／集積化技術

11:30 〜 11:45英語発表

[15a-M_124-10] Study on Design-Technology Co-Optimization for Complementary FET Logic

〇(D)Yuxuan Wang¹, Yaoping Xiao¹, Jinhyun Chun¹, Xiaoran Mei¹, Takuya Saraya¹, Toshiro Hiramoto¹, Masaharu Kobayashi¹ (1.IIS, The University of Tokyo)

キーワード：

DTCO、CFET

Complementary FET (CFET) has emerged as a promising technology to further improve cell density beyond conventional gate-all-around (GAA) nanosheet FET scaling. We provide an integrated design-technology co-optimization (DTCO) methodology to quantify realistic power-performance trade-offs for CFET devices and standard cells, and demonstrates the trade-offs through comparative standard cells evaluations under different design options.