講演情報
[15a-M_124-11]Design–Technology Co-Optimization (DTCO) for Inner-Spacer Length Design
in Nanosheet Standard Cells Using a Pseudo Logic-Block Gauge
〇(D)Xiaoran Mei1, Yaoping Xiao1, Takuya Saraya1, Toshiro Hiramoto1, Masaharu Kobayashi1,2 (1.IIS, Univ. of Tokyo, 2.d.lab, Univ. of Tokyo)
キーワード：
Nanosheet、DTCO、Inner Spacer
CMOS logic scaling is limited by lithography/patterning, motivating gate-all-around (GAA) nanosheet (NS) FETs as a FinFET successor, while backside power delivery (BSPDN), such as PowerVia and backside contact (BSC), improves power delivery efficiency against conventional frontside (FS) PDN. At advanced nodes, the co-variation of parasitic capacitance and contact resistance becomes a dominant limiter, and the inner-spacer length (Lis) simultaneously modulates device current (Ion), parasitic capacitance (Cpara) and contact resistance (Rcon) via S/D epi length (Lsd), effective gate length (Lgeff) and contact length (Lcon). Here we implement a GAA NS FET inverter with extracted parasitics and use an empirical pseudo logic-block power-delay product (PDP) / energy-delay product (EDP) gauge to evaluate Lis trends under FS and BSC PDNs, with 15-stage fanout-3 (FO3) ring oscillator (RO) as reference. Through the evaluation, we explored the opportunity of Design-Technology-Co-Optimization in GAA NS FET design.