講演情報
[15a-WL2_301-3]Systematic Modeling and Optimization of TSV Sidewall Geometry via FDTD Simulation and Factor Response Analysis
〇(M2)Chia-Yu Huang1, Chih-Chung Wang1, Song-En Chen1, Jia-Han Li1 (1.National Taiwan University)
キーワード：
Through-Silicon Via (TSV)、FDTD Simulation
Chip on Wafer on Substrate (CoWoS) is a key advanced packaging technology for AI chips, where accurate metrology of high–aspect-ratio Through-Silicon Vias (TSVs) remains challenging. Variations in TSV sidewall and bottom geometry can significantly alter reflected spectra, making reliable simulation essential for optical inspection. In this study, a systematic framework is proposed to model and optimize TSV sidewall geometry using full-wave electromagnetic simulations. The geometry is parameterized by the radius of curvature of smooth arc segments, the number of discretized layers, and the z-direction radius of the bottom ellipsoid. A full factorial design of experiments combined with finite-difference time-domain (FDTD) simulations is employed to generate reflection spectra. The discrepancy between simulated and measured spectra is quantified using root mean square error (RMSE), and a smaller-is-better signal-to-noise ratio is applied for factor response analysis. The optimal parameter combination and the most influential geometric factors are identified, enabling efficient construction of an accurate simulation database for TSV optical metrology.