[17a-S2_203-1~12] 13.5 デバイス／配線／集積化技術

11:30 〜 11:45英語発表

[17a-S2_203-10] Process development for fabricating Si nanosheet GAAFET on 300 mm wafers: Selective epitaxial growth and channel release

〇CHIATSONG CHEN¹, Toshihiro Narushima¹, Shin Kono¹, Kazuya Uejima¹, Atsushi Yagishita¹, Naoto Kumagai¹, Takahiro Goya¹, Ryutaro Nishino¹, Kenzou Manabe¹, Yoko Tanaka¹, Masanaga Fukasawa¹, Yuuki Ishida¹, Yukinori Morita¹, Hiroyuki Ota¹, Toshifumi Irisawa¹, Wataru Mizubayashi¹, Takashi Matsukawa¹, Yoshihiro Hayashi¹ (1.AIST)

キーワード：

Si transistor、selective epitaxy、channel release

In this study, we fabricated n- and p-channel NS GAAFETs [1] on 300 mm wafers by optimizing the fabrication process conditions including the source/drain epitaxy and selective SiGe etching. This provides guidelines to address issues of abnormal epitaxial growth and residual Ge in NS channels.