[14a-K101-1~10] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

10:45 AM - 11:00 AM JST(1:45 AM - 2:00 AM UTC)Presentation by Applicant for JSAP Young Scientists Presentation Award

[14a-K101-5] Evaluation of Low-Temperature Characteristics of High-Voltage Transistors in Cryo-CMOS for Superconducting Qubit Control

〇(B)Seibun Oshio¹, Mizuki Kobayashi¹, Kazuki Adachi¹, Ryousuke Hyashi¹, Keito Yoshinaga², Ken Uchida², Munehiro Tada¹ (1.Keio Univ, 2.Tokyo Univ)

Keywords:

semiconductor,Cryo-CMOS

This study evaluates the ultra-low temperature characteristics of HV-nMOSFETs (rated 2.5V) in 65nm CMOS technology, including measurements under overdrive conditions. At 4K, an increase in Id and an abnormal rise in saturation current near the threshold voltage (Vth) were observed. These phenomena are attributed to impact ionization and freeze-out effects in the substrate, leading to high substrate resistance. Additionally, trapped holes in the substrate caused a positive body bias effect, which lowered Vth. Under overdrive conditions, these effects were further enhanced due to the strong electric field. The Id-Vg characteristics revealed low leakage, high Vth, and other features unique to low temperatures. However, hysteresis was observed at high drain voltages, likely caused by Joule heating during return measurements. This heating increased the local temperature, suppressing substrate trapping and altering the characteristics. These findings provide insights into the behavior of HV transistors under cryogenic conditions and are critical for the development of cryogenic CMOS control circuits for quantum computing applications.