Presentation Information
[15p-K101-5]2.xD/3D Integration & Packaging Technology
〇Yoichiro Kurita1 (1.Institute of Science Tokyo)
Keywords:
Chiplet,3D Integration
In semiconductor integrated circuit technology, the limits of integration scale and integration density, such as the slowdown of Moore's law and the von Neumann bottleneck, have become performance and power bottlenecks in applications such as artificial intelligence (AI). Chiplet integration technology, which has the potential to optimally and scalably expand the capability by integrating many chips with different manufacturing methods, functions, and structures while maintaining the connection bandwidth between integrated circuit chips, is attracting attention as a promising method to solve these issues. This presentation will review the origins and limitations of integrated circuit technology to date and the history of research and development of 2.xD/3D integration technology to complement this technology. Then, the current state-of-the-art developments, applications, and challenges will be described, and R&D activities including chiplet integration platforms (2.xD integration), 3D integration, and optical integration in the Chiplet Integration Platform Consortium led by the Institute of Science Tokyo will be introduced.
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