[17a-K101-1~13] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

10:00 AM - 10:15 AM JST(1:00 AM - 1:15 AM UTC)

[17a-K101-5] Local interconnect process using nanoimprint lithography

〇Kenta Suzuki¹, Tetsuya Ueda¹, Yuji Kasashima¹, Masanaga Fukasawa¹, Hiroshi Hiroshima¹, Yoshihiro Hayashi¹, Masaki Ishida², Tomomi Funayoshi², Hiromi Hiura², Masayuki Kagawa², Noriyasu Hasegawa², Kiyohito Yamamoto² (1.SFRC, AIST, 2.Canon)

Keywords:

Logic semiconductor,Nanoimprint lithography,damascene interconnect

Nanoimprint lithography(NIL) has recently been attracting attention as a green lithographic technology. In this work, a test pattern with a minimum pitch of 48 nm was fabricated using NIL, and W damascene interconnect processes. The electrical performances of the test devices were subsequently evaluated using the open/short test element group.