[17p-K103-1~9] 13.4 Si processing /Si based thin film / MEMS / Equipment technology

2:00 PM - 2:15 PM JST(5:00 AM - 5:15 AM UTC)

[17p-K103-3] Study of resist etch-back planarization process using Minimal Fab equipment

〇Hiroyuki Tanaka¹, Shunichiro Shinbori², Satoshi Takahashi², Hiroshige Kogayu¹, Noriko Miura¹, Shinichi Ikeda¹, Shiro Hara^1,3 (1.AIST, 2.SUNYOU, 3.HS)

Keywords:

planarization,etchback,Wiring Process

In the process of developing integrated circuits, it has become clear that the formation of wiring between elements requires overcoming the step between device islands, and that this makes it easy for the wiring to break at the step. In this report, we report on our investigation into a technology for etching back the TEOS (Tetraethyl orthosilicate) surface to a flat surface, devising a process in which the etching rate of the resist and TEOS film is 1:1, without using CMP, by depositing TEOS on the island and then etching it.