The 72nd JSAP Spring Meeting 2025
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Session Details

Symposium (Oral)Symposium : Frontiers in Low-Power Semiconductor Technologies: Paving the Way for Carbon Neutrality

[16p-K205-1~10]Frontiers in Low-Power Semiconductor Technologies: Paving the Way for Carbon Neutrality

Sun. Mar 16, 2025 1:00 PM - 5:30 PM JST
Sun. Mar 16, 2025 4:00 AM - 8:30 AM UTC
K205 (Lecture Hall Bldg.)
Masaharu Kobayashi(Univ. of Tokyo), Mitsuru Takenaka(Univ. of Tokyo), Masahiro Nomura(Univ. of Tokyo)
1:00 PM - 1:05 PM JST(4:00 AM - 4:05 AM UTC)

[16p-K205-1]Opening

〇Masahiro Nomura1 (1.UTokyo)
Comment()
1:05 PM - 1:35 PM JST(4:05 AM - 4:35 AM UTC)

[16p-K205-2]Technology Trends of Advanced Logic Devices and Activities of LSTC

〇Toshiro Hiramoto1, Hitoshi Wakabayashi2 (1.IIS, UTokyo, 2.Science Tokyo)
Comment()
1:35 PM - 2:05 PM JST(4:35 AM - 5:05 AM UTC)

[16p-K205-3]CMOS annealing machine solving optimization problems with low power consumption

〇Masanao Yamaoka1 (1.Hitachi)
Comment()
2:05 PM - 2:35 PM JST(5:05 AM - 5:35 AM UTC)

[16p-K205-4]Recent progresses in fundamental technologies of 3D nanowire integrated circuit with ultra low-power consumption

〇Katsuhiro Tomioka1, Kohei Hamaya2, Koji Inoue3 (1.GS-IST & RCIQE, Hokkaido Univ., 2.GS-ES, CSRN & OTRI, Osaka Univ, 3.GS-ISEE, Kyusyu Univ.)
Comment()
2:50 PM - 3:20 PM JST(5:50 AM - 6:20 AM UTC)

[16p-K205-5]Present and Future Perspectives on Wafer-Scale Integration of 2D Materials

〇Kosuke Nagashio1 (1.UTokyo)
Comment()
3:20 PM - 3:50 PM JST(6:20 AM - 6:50 AM UTC)

[16p-K205-6]Thermal Management of Semiconductor Devices by Phonon Engineering

〇Junichiro Shiomi1 (1.The Univ. of Tokyo)
Comment()
3:50 PM - 4:05 PM JST(6:50 AM - 7:05 AM UTC)

[16p-K205-7]Study on 3D chiplets with excellent heat dissipation using high thermal conductivity insulator AlN film

〇Takeshi Takagi1, Takeki Ninomiya1, Masaaki Niwa1, Tadahiro Kuroda1 (1.The Univ. of Tokyo)
Comment()
4:20 PM - 4:50 PM JST(7:20 AM - 7:50 AM UTC)

[16p-K205-8]Collaboration with Heterogeneous Device and Material Technologies in Integrated Power Supply Systems

〇Kousuke Miyaji1 (1.Shinshu Univ.)
Comment()
4:50 PM - 5:20 PM JST(7:50 AM - 8:20 AM UTC)

[16p-K205-9]3D integrated packaging technology for device integration and low power consumption

〇Katsuya Kikuchi1 (1.AIST)
Comment()
5:20 PM - 5:30 PM JST(8:20 AM - 8:30 AM UTC)

[16p-K205-10]Closing

〇Tadahiro Kuroda1 (1.The Univ. of Tokyo)
Comment()
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