[3B01-11] Low-dimensional Material / Nanostructure / Nanomaterial (LD/NS/NM))

11:15 AM - 11:30 AM JST(2:15 AM - 2:30 AM UTC)

[3B08] Demonstration of Monoatomic-Gate-Length MoS2 Transistors using Orthogonal Graphene/MoS₂ Heterostacks

Hirai Tanaka¹, Fuminori Sasaki¹, Qiyue He¹, Hideaki Sugino¹, Kazuki Yonekubo¹, Toshifumi Irisawa², Naoya Okada², Akiko Ueda², Takahiro Iizuka³, Takeo Matsuki⁴, Daisuke Ohori⁵, Kazuhiko Endo⁶, Keisuke Atsumi⁷, Kosuke Nagashio⁷, Issei Watanabe⁸, *hirokazu fukidome¹ (1. RIEC, Tohoku Univ. (Japan), 2. AIST (Japan), 3. Hiroshima Univ. (Japan), 4. Univ. Tsukuba (Japan), 5. Kansai Univ (Japan), 6. IFS, Tohoku Univ. (Japan), 7. The Univ. Tokyo (Japan), 8. NICT (Japan))

Ultrascaled transistors with atomically short gates are crucial for next-generation wireless systems but face severe short-channel and lithographic limitations. Utilizing the edge of a highly conductive 2D crystal as a gate against a transition-metal dichalcogenide channel is a promising scaling strategy. In this study, we demonstrate the gate-controlled DC operation of a monoatomic-gate-length MoS₂ transistor utilizing an orthogonal graphene/MoS₂ heterostack. Epitaxial graphene on SiC was patterned into a nanoscale step, across which MoS₂ channels were orthogonally formed. Angled deposition enabled an ultra-short source/drain spacing of approximately 125 nm. The drain current density is systematically modulated by gate voltage, reaching 11 μA/μm at +2 V, which is significantly higher than previous reports. This work establishes a vertical-stack platform for ultimately scaled 2D transistors toward Beyond-5G applications without relying on advanced top-down lithography.

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