[C-12] Integrated Circuit and Devices | IEICE Society Conference 2026

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Session Details

一般セッションC. Electronics Society : C-12．Integrated Circuit and Devices

[C-12]Integrated Circuit and Devices

Wed. Sep 23, 2026 9:00 AM - 12:00 PM JST
Wed. Sep 23, 2026 12:00 AM - 3:00 AM UTC

C-Bldg C207(Hokkaido University)

Chair:TORU SAI, Okada Kenichi

9:00 AM - 9:30 AM JST(12:00 AM - 12:30 AM UTC)

[C-12-01]Pioneering Research on High-Precision and High-Efficiency Analog Integrated Circuit Design Technologies

〇Tetsuya Iizuka¹ (1. The University of Tokyo)

9:30 AM - 9:45 AM JST(12:30 AM - 12:45 AM UTC)

[C-12-02]Digital Trimming of Clock Generator for Third-order CIFF Delta-Sigma Modulator for isolated ADC

〇Jun Tomisawa¹, Shota Morisaki¹ (1. Mitsubishi Electric Corp.)

9:45 AM - 10:00 AM JST(12:45 AM - 1:00 AM UTC)

[C-12-03]Design of Multi-Frequency-Band Upconversion Paths for Wideband Frequency-Interleaved DAC

〇WENTIAN HOU¹, Yunjie Chen¹, Koji Asami², Ritaro Takenaka¹, Sota Kano¹, Zolboo Byambadorj², Masahiro Ishida³, Tetsuya Iizuka¹ (1. Department of Electrical Engineering and Information Systems, School of Engineering, The University of Tokyo, 2. Systems Design Lab, The University of Tokyo, 3. Advantest Corporation)

10:00 AM - 10:15 AM JST(1:00 AM - 1:15 AM UTC)Candidate for Academic Incentive Award

[C-12-04]低電源電圧・低消費電力スタンダードセルベースコンパレータのオフセットキャンセル技術

◎Koki Kiyota¹, Yoshimori Kaneshiro¹ (1. Osaka Institute of Technology)

10:15 AM - 10:30 AM JST(1:15 AM - 1:30 AM UTC)Candidate for Academic Incentive Award

[C-12-05]A DLL Control Scheme for Arrival Timing Correction in In-Vehicle Frame-Signal Transmission

◎Shoma Takizawa¹, Toshiyuki Inoue², Akira Tsuchiya³, Shin-ichi Sakamoto¹, Satoshi Hirayama¹ (1. The University of Shiga Prefecture, 2. Kyoto Institute of Technology, 3. Kansai University)

10:30 AM - 10:45 AM JST(1:30 AM - 1:45 AM UTC)

Break time

10:45 AM - 11:00 AM JST(1:45 AM - 2:00 AM UTC)Candidate for Academic Incentive Award

[C-12-06]Unmet-Specification-Aware Genetic Algorithm Based on Contribution Analysis for Analog Design Automation

◎Hijiri Fujiwara¹, Akira Tsuchiya², Toshiyuki Inoue³, Shigeyuki Miyagi¹ (1. The University of Shiga Prefecture, 2. Kansai University, 3. Kyoto Institute of Technology)

11:00 AM - 11:15 AM JST(2:00 AM - 2:15 AM UTC)Candidate for Academic Incentive Award

[C-12-07]Improvement of Line Regulation in Cryogenic Voltage Reference Circuit Using a Nagata Current Mirror

◎Koki Takehisa¹, Akira Tsuchiya², Toshiyuki Inoue³, Junichi Yanagisawa¹ (1. The University of Shiga Prefecture, 2. Kansai University, 3. Kyoto Institute of Technology)

11:15 AM - 11:30 AM JST(2:15 AM - 2:30 AM UTC)Candidate for Academic Incentive AwardCareer Explorer

[C-12-08]Feasibility Study of a Digitally Controlled FBAR Oscillator for Chip-Scale Atomic Clocks

◎△Kazutoshi Nishio¹, Masahiro Fukuoka¹, Motoaki Hara², Dosho Shiro¹, Ito Hiroyuki¹ (1. Institute of Science Tokyo, 2. National Institute of Information)

11:30 AM - 11:45 AM JST(2:30 AM - 2:45 AM UTC)

[C-12-09]A low-power wide-range duty cycle controller based on pulse modification for time-division RF circuits

〇HAIYUN GU¹, Dongfan Xu¹, Minzhe Tang¹, Yuxuan Liu¹, Ziyuan Ren¹, Yilun Chen¹, Minghao Fan¹, Duo Li¹, Zheng Li¹, Yi Zhang¹, Daxu Zhang¹, Zezheng Liu¹, Chun Wang¹, Yudai Yamazaki¹, Hiroyuki Sakai¹, Yuncheng Zhang¹, Kazuaki Kunihiro¹, Kenichi Okada¹ (1. Institute of Science Tokyo)

11:45 AM - 12:00 PM JST(2:45 AM - 3:00 AM UTC)

[C-12-10]Evaluation of Transmitted-Reference Signaling for 2.4-GHz Wake-Up Receivers under Wi-Fi OFDM Interference

〇Xinyu Tao¹, Kazutoshi Nishio¹, Ryota Toda¹, Shiro Dosho¹, Hiroyuki Ito¹ (1. Nano Sensing Research Unit, Institute of Integrated Research, Institute of Science Tokyo)

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