International Conference on Solid State Devices and Materials

Vertically stacking nanosheet devices enables sustained area scaling without penalty on device perimeter by virtue of separating nFET and pFET devices in the vertical direction. Adopting this complementary FET (CFET) architecture implies innovations in the middle of line (MOL) are needed to form the intracell source/drain contacts and to form intercell connections without losing the area benefit while maintaining low access resistance. The merits of connecting into the CFET bottom device from the wafer backside and of a VHV patterning style to avoid congestion at wire out are discussed in this paper.