2024 International Conference on Solid State Devices and Materials
Sep 1 - Sep 4, 2024Arcrea HIMEJI
2024 International Conference on Solid State Devices and Materials
Sep 1 - Sep 4, 2024Arcrea HIMEJI
[A-1-03]Demonstration of Poly Gate Cut Process at Tight Gate Pitch of 50nm and High Gates Aspect Ratio for Advanced Device Architectures
〇Xiuju Zhou1, Zheng Tao 1, Hans Mertens1, Emmanuel Dupuy1, Anabela Veloso1, Boon Teik Chan1, Sujith Subramanian1, Naoto Horiguchi1, Serge Biesemans1, Elisabeth Camerotto2, Haseeb Kazi2, Ziad El Otell2(1. IMEC (Belgium), 2. Lam Res. Corp. (United States of America))
This work reports the development of a poly gate cut (PGC) process using dry etch at a tight contacted poly pitch (CPP) of 50nm with high gates aspect ratio (HAR) >10, suitable for advanced device architectures, including nanosheet (NS) FETs and 3D stacked complementary field-effect transistor (CFET). High selectivity to gate spacers and zero-level interlayer dielectric (ILD0) oxide is achieved with dry etch optimization. a-Si dummy gate at cut area was successfully pulled without residues at the trench bottom or at its sidewalls, while a straight profile was maintained. Different plug filling materials were investigated after PGC etch, addressing the challenges for HAR-trench filling. Finally, good process integrity after replacement metal gate (RMG) module implementation was successfully demonstrated.