[A-4-04 (Late News)]Low-temperature annealing effect on electrical/structural characteristics for SiO2/GeO2/Ge gate stack
〇Hajime Kuwazuru1, Taisei Aso1, Dong Wang2, Keisuke Yamamoto2(1. IGSES, Kyushu Univ. (Japan), 2. FES, Kyushu Univ. (Japan))
We studied the effect of low-temperature annealing for a SiO2/GeO2/Ge gate stack. Low-temperature annealing decreases the Ge suboxide (GeOx) formation in the GeO2 layer. As a result, flatband voltage shifted to a positive direction due to the decreasing interface dipole caused by oxygen atom movement at a SiO2/GeO2 interface. We also characterized the interface state density (Dit) and border trap density (Nbt) in the SiO2/GeO2/Ge gate stack using the deep level transient spectroscopy. Low-temperature annealing decreases the Dit and Nbt in near SiO2/GeO2 interface; it is suggested that GeOx formation generates the interface trap and border trap.
