Presentation Information
[A-4-04 (Late News)]Low-temperature annealing effect on electrical/structural characteristics for SiO2/GeO2/Ge gate stack
〇Hajime Kuwazuru1, Taisei Aso1, Dong Wang2, Keisuke Yamamoto2 (1. IGSES, Kyushu Univ. (Japan), 2. FES, Kyushu Univ. (Japan))