Session Details
[A-4]Advanced CMOS: Device Technology
Tue. Sep 3, 2024 10:45 AM - 12:15 PM JST
Tue. Sep 3, 2024 1:45 AM - 3:15 AM UTC
Tue. Sep 3, 2024 1:45 AM - 3:15 AM UTC
Room A (407)(4th Floor)
Session Chair: Anabela Veloso (imec), Keisuke Yamamoto (Kyushu Univ.)
[A-4-01]High Performance (111)-Oriented Extremely-Thin Body Ge-On-Insulator nMOSFETs down to 2.1 nm
〇Xueyang Han1, Chia-Tsong Chen1, Kei Sumita1, Kasidit Toprasertpong1, Mitsuru Takenaka1, Shinichi Takagi1 (1. The University of Tokyo (Japan))
[A-4-02]Electron Transport in Ge(Sn) n-type Metal-Oxide-Semiconductor Field-Effect Transistors at Cryogenic Temperatures
〇Yen-Yang Chen1, Kai-Ying Tien1, Chia-You Liu1, Wei-Hsiang Kao1, Jiun-Yun Li1,2 (1. National Taiwan Univ. (Taiwan), 2. Taiwan Semiconductor Res. Inst. (Taiwan))
[A-4-03]Te-based layered materials for Fermi-level Depinning on n-Ge
〇Wen Hsin CHANG1, Shogo HATAYAMA1, Naoya OKADA1, Toshifumi IRISAWA1, Yuta SAITO1,2 (1. AIST (Japan), 2. Tohoku Univ. (Japan))
[A-4-04 (Late News)]Low-temperature annealing effect on electrical/structural characteristics for SiO2/GeO2/Ge gate stack
〇Hajime Kuwazuru1, Taisei Aso1, Dong Wang2, Keisuke Yamamoto2 (1. IGSES, Kyushu Univ. (Japan), 2. FES, Kyushu Univ. (Japan))
[A-4-05]Determining factors of the Effective Work Function of TiN/TiAlC Metal Gates for Advanced Gate-all-around CMOS Integration
〇Kenzo Manabe1, Kazuya Uejima1, Hiroyuki Ota1, Yukinori Morita1, Toshifumi Irisawa1, Yoshihiro Hayashi1 (1. National Inst. of Advanced Indus. Sci. and Tech. (Japan))
[A-4-06]Gate-All-Around Vertical Channel Transistor Based on Self-Aligned in 2 Pitch Process for Future DRAM
〇Seunguk Han1 (1. Samsung electronics Co., Ltd. (Korea))