2024 International Conference on Solid State Devices and Materials
Sep 1 - Sep 4, 2024Arcrea HIMEJI
2024 International Conference on Solid State Devices and Materials
Sep 1 - Sep 4, 2024Arcrea HIMEJI
[A-6-05]Assessment and optimization of the cascaded transistor method for the direct extraction of access resistance components in FinFET and NSFET devices.
〇Pierre Eyben1, An De Keersgieter1, Philippe Matagne1, Hans Mertens1, Thomas Chiarella1, Clément Porret Porret1, Camila Toledo de Carvalho Cavalcante1, Yong Kong Siew1, Jerome Mitard1, Naoto Horiguchi1(1. Imec (Belgium))
In this work, we have built calibrated TCAD decks for FinFET and NSFET devices, respectively, to validate our access resistance extraction method based on cascaded transistor test-structures. Besides the validation of the approach, we also propose an improved measurement set-up. Finally, we present some initial results from n-NSFET devices with 45 nm contacted poly pitch and 20 nm gate length, analyzing the impact of spike annealing steps.