[A-6] Modeling, Simulation and Characterization | 2024 International Conference on Solid State Devices and Materials

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Session Details

Oral Presentation01: Advanced CMOS: Material Science / Process Engineering / Device Technology

[A-6]Modeling, Simulation and Characterization

Wed. Sep 4, 2024 10:45 AM - 12:15 PM JST
Wed. Sep 4, 2024 1:45 AM - 3:15 AM UTC

Room A (407)(4th Floor)

Session Chair: Pin Su (NYCU), Nobuyuki Mise (Hitachi High-Tech Corp.)

10:45 AM - 11:15 AM JST(1:45 AM - 2:15 AM UTC)Invited

[A-6-01 (Invited)]Milli-Kelvin Analysis Revealing the Role of Band-edge States in Cryogenic MOSFETs

〇Hiroshi Oka¹, Hidehiro Asai¹, Takumi Inaba¹, Shunsuke Shitakata¹, Hitoshi Yui¹, Hiroshi Fuketa¹, Shota Iizuka¹, Kimihiko Kato¹, Takashi Nakayama¹, Takahiro Mori¹ (1. National Institute of Advanced Industrial Science and Technology (AIST) (Japan))

11:15 AM - 11:30 AM JST(2:15 AM - 2:30 AM UTC)

[A-6-02]Comparative Analysis of Cryogenic Threshold Voltage and On-current Variability in 65nm Bulk and FDSOI MOSFETs

〇Zihao Liu¹, Tomoko Mizutani¹, Kiyoshi Takeuchi¹, Takuya Saraya¹, Hiroshi Oka², Takahiro Mori², Masaharu Kobayashi¹, Toshiro Hiramoto¹ (1. The Univ. of Tokyo (Japan), 2. The National Inst. of Advanced Indus. Sci. and Tech. (Japan))

11:30 AM - 11:45 AM JST(2:30 AM - 2:45 AM UTC)

[A-6-03]Accurate Evaluation of Effective Mobility in Si nMOSFETs at Cryogenic Temperature by Introducing Quasi-Static C-V Method

〇Yutong Chen¹, Zhao Jin¹, Xueyang Han¹, Hiroshi Oka², Takahiro Mori², Kasidit Toprasertpong¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1. The Univ. of Tokyo (Japan), 2. National Inst. of Advanced Indus. Sci. and Tech. (Japan))

11:45 AM - 12:00 PM JST(2:45 AM - 3:00 AM UTC)

[A-6-04]A Correction Method of Split C-V Characteristics in MOSFETs by Using Transmission Line Model for Accurate Extraction of Effective Mobility

〇Zhao Jin¹, Yutong Chen¹, Xueyang Han¹, Hiroshi Oka², Takahiro Mori², Kasidit Toprasertpong¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1. The Univ. of Tokyo (Japan), 2. National Inst. of Advanced Indus. Sci. and Tech. (Japan))

12:00 PM - 12:15 PM JST(3:00 AM - 3:15 AM UTC)

[A-6-05]Assessment and optimization of the cascaded transistor method for the direct extraction of access resistance components in FinFET and NSFET devices.

〇Pierre Eyben¹, An De Keersgieter¹, Philippe Matagne¹, Hans Mertens¹, Thomas Chiarella¹, Clément Porret Porret¹, Camila Toledo de Carvalho Cavalcante¹, Yong Kong Siew¹, Jerome Mitard¹, Naoto Horiguchi¹ (1. Imec (Belgium))

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