International Conference on Solid State Devices and Materials

A channel resistance is one of the dominant resistive components in a GaN metal–oxide–semiconductor field-effect transistor (MOSFET) having a breakdown voltage of 1.7 kV or less. The gate stack of an AlSiO/AlN/p-type GaN has demonstrated an enough time-to-dielectric-breakdown, a high channel mobility, and a stability of the threshold voltage (V_th) under a positive gate bias. The key is the interface engineering using a crystalline AlN interlayer formed by plasma-enhanced atomic layer deposition. The AlN interlayer enhances the channel mobility and the V_th stability, while reduces the V_th due to the polarization charge at the AlN/GaN interface on the c-plane. By forming an electron inversion channel on a m-plane trench, a channel mobility of 150 cm² V^–1s^–1 and an enhancement mode operation (V_th = 1.3 V) are simultaneously demonstrated.