[F-2] Thermoelectric materials and devices II

4:30 PM - 4:45 PM JST(7:30 AM - 7:45 AM UTC)

[F-2-02] Optimizing the Wiring Layout of Silicon Integrated Thermoelectric Devices for Enhancing Maximum Performance

〇Md Mehdee Hasan Mahfuz¹, Suhei Arai¹, Takeo Matsuki¹, Watanabe Takanobu¹ (1. Waseda University (Japan))

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