Session Details
[F-2]Thermoelectric materials and devices II
Mon. Sep 2, 2024 4:15 PM - 5:30 PM JST
Mon. Sep 2, 2024 7:15 AM - 8:30 AM UTC
Mon. Sep 2, 2024 7:15 AM - 8:30 AM UTC
Room F (402)(4th Floor)
Session Chair: Shinnya Kato (Nagoya Inst. of Technology), Takuya Hoshii (Tokyo Tech)
[F-2-01]Reduction of Thermal Conductivity in Silicon Thin Film by Super-lattice Interface and Phononic Crystal Nanostructures
Sota Koike1, Ryoto Yanagisawa1, Takahiro Inoue2, Kentarou Sawano2, 〇Masahiro Nomura1 (1. Inst. of Indus. Sci., the Univ. of Tokyo (Japan), 2. Tokyo City Univ. (Japan))
[F-2-02]Optimizing the Wiring Layout of Silicon Integrated Thermoelectric Devices for Enhancing Maximum Performance
〇Md Mehdee Hasan Mahfuz1, Suhei Arai1, Takeo Matsuki1, Watanabe Takanobu1 (1. Waseda University (Japan))
[F-2-03]Scaling Effect of Silicon-based Micro Thermoelectric Device with Cavity
〇Takuya Miura1, Md Mehdee Hasan Mahfuz1, Takeo Matsuki1, Takanobu Watanabe1 (1. Waseda Univ. (Japan))
[F-2-04]Identification of Temperature Difference Across the Thermoelements of an Integrated Micro Thermoelectric Device
〇Ryuichiro Arayama1, Takuya Miura1, Md Mehdee Hasan Mahfuz1, Takeo Matsuki1, Takanobu Watanabe1 (1. Waseda Univ. (Japan))
[F-2-05]Thermoelectric properties of CMOS-compatible GeSn binary alloys at room temperature
〇Jhonny Tiscareno Ramirez1, Omar Concepción1, Thomas Classen1, Zoran Ikonic2, Francisco Rivadulla3, Detlev Grützmacher1, Dan Buca1 (1. PGI-9 Forschungszentrum Jülich (Germany), 2. Univ. of Leeds (UK), 3. Univ. de Santiago de Compostela (Spain))