[A-1] CFET Technology

1:30 PM - 2:00 PM JST(4:30 AM - 5:00 AM UTC)

[A-1-01 (Invited)] Modeling of Transistor and Interconnect Technologies Targeting Next Generation Logic GAA and CFET Nodes

〇Ashish Pal¹, Pratik B. Vyas¹, Gregory Costrini¹, El Mehdi Bazizi¹ (1. AMAT (United States of America))