2025 International Conference on Solid State Devices and Materials
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Session Details

Oral Presentation01: Advanced CMOS: Material Science / Process Engineering / Device Technology

[A-1]CFET Technology

Tue. Sep 16, 2025 1:30 PM - 3:15 PM JST
Tue. Sep 16, 2025 4:30 AM - 6:15 AM UTC
Room A (301, 3rd Floor)
Session Chair: Takashi Matsukawa (AIST), Kuniyuki Kakushima (Science Tokyo)
1:30 PM - 2:00 PM JST(4:30 AM - 5:00 AM UTC)

[A-1-01 (Invited)]Modeling of Gate-All-Around and CFET Transistor and Interconnects towards Next Generation Logic Nodes

〇Ashish Pal1 (1. AMAT (United States of America))
2:00 PM - 2:15 PM JST(5:00 AM - 5:15 AM UTC)

[A-1-02]Ultimate Scaling of the Bonding Dielectric for sequential CFET

〇ANNE VANDOOREN1, Kevin Vandersmissen1, Ferenc Fodor1, Gerhard Bast2, Jeffrey Mileham2, Steven Demuynck1, Katia Devriendt1, Naoto Horiguchi1, Serge Biesemans1 (1. imec (Belgium), 2. KLA Corporation (United States of America))
2:15 PM - 2:30 PM JST(5:15 AM - 5:30 AM UTC)

[A-1-03]Recent insights in direct extraction of access resistance components in NSFET and CFET devices with the cascaded transistor method

〇PIERRE CHARLES EYBEN1, Andrea Pondini1,2, Hiroaki Arimura1, Thomas Chiarella1, Hans Mertens1, Clément Porret1, Erik Rosseel1, Ritam Sarkar1, Maryam Hosseini1, Daisy Zhou1, Jérome Mitard1, Naoto Horiguchi1 (1. IMEC (Belgium), 2. KU Leuven (Belgium))
2:30 PM - 2:45 PM JST(5:30 AM - 5:45 AM UTC)

[A-1-04]Comparative Analysis of Conventional and Line-Type Tall Via Structures for CFET: Performance, Scalability, and Process Feasibility

〇Jimyoung Lee1,2, Seung Kyu Kim1,2, KwangYoung Lee1,2, Jongwook Jeon1 (1. Sungkyunkwan Univ. (Korea), 2. Samsung Electronics (Korea))
2:45 PM - 3:00 PM JST(5:45 AM - 6:00 AM UTC)

[A-1-05]Evaluation of SiCO as a Protective Layer for Nanosheet Integrity and Random Parasitic Channel Mitigation in Monolithic Complementary FET Fabrication

〇Yu-Fan (Andy) Peng1, Steven Demuynck1, Camila Toledo de Carvalho Cavalcante1, Jishnu Ganguly1, Cassie Sheng1, Karen Stiers1, Anne Vandooren1, Maryam Hosseini1, Dmitry Batuk1, Thomas Chiarella1, Anthony Peter1, Maria Chistiakova1, Alfonso Marquez1, Lucas PetersenBarbosa Lima1, Naoto Horiguchi1, Serge Biesemans1 (1. IMEC (Belgium))
3:00 PM - 3:15 PM JST(6:00 AM - 6:15 AM UTC)

[A-1-06]Defect Characterization through Fin and Gate Modules for Complementary Field-Effect Transistor Fabrication

〇Xiuju Zhou1, Nachiketa Zhou Janardan1, Andrea Mingardi1, Ataklti Weldeslassie1, Anabela Veloso1, Lucas Petersen Barbosa Lima1, Serge Biesemans1, Kaushik Sah2, Roel Gronheid2, Andrew Cross2 (1. IMEC (Belgium), 2. KLA Corp. (United States of America))
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