[A-1] CFET Technology

2:30 PM - 2:45 PM JST(5:30 AM - 5:45 AM UTC)

[A-1-04] Comparative Analysis of Conventional and Line-Type Tall Via Structures for CFET: Performance, Scalability, and Process Feasibility

〇Jimyoung Lee^1,2, Seung Kyu Kim^1,2, KwangYoung Lee^1,2, Jongwook Jeon¹ (1. Sungkyunkwan Univ. (Korea), 2. Samsung Electronics (Korea))