[A-6] Integration Technology on Si Wafer

11:30 AM - 11:45 AM JST(2:30 AM - 2:45 AM UTC)

[A-6-03] Room temperature operation of Ge_1−xSn_x/Ge_1−x−ySi_xSn_y resonant tunneling diode

〇Shota Torimoto¹, Shuto Ishimoto¹, Yoshiki Kato¹, Mitsuo Sakashita¹, Masashi Kurosawa¹, Osamu Nakatsuka^1,2, Shigehisa Shibayama¹ (1. Grad. Sch. of Eng., Nagoya Univ. (Japan), 2. IMaSS, Nagoya Univ. (Japan))