[A-6] Integration Technology on Si Wafer | 2025 International Conference on Solid State Devices and Materials

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Session Details

Oral Presentation01: Advanced CMOS: Material Science / Process Engineering / Device Technology

[A-6]Integration Technology on Si Wafer

Thu. Sep 18, 2025 10:45 AM - 12:00 PM JST
Thu. Sep 18, 2025 1:45 AM - 3:00 AM UTC

Room A (301, 3rd Floor)

Session Chair: Shoichi Kabuyanagi (KIOXIA), Shibun Tsuda (Renesas Electronics Corp.)

10:45 AM - 11:15 AM JST(1:45 AM - 2:15 AM UTC)

[A-6-01 (Invited)]Oxide semiconductors for future DRAM and monolithic 3D integration

Kexin Wang¹, 〇Jianshi Tang¹ (1. Tsinghua Univ. (China))

11:15 AM - 11:30 AM JST(2:15 AM - 2:30 AM UTC)

[A-6-02]Laser annealing technology for storage node contact in graphic DRAMs

〇Dongkyu Jang¹, Jieun Lee¹, Taehoon Park¹, Chanho Park¹, Hyodong Ban¹ (1. Samsung Electronics (Korea))

11:30 AM - 11:45 AM JST(2:30 AM - 2:45 AM UTC)

[A-6-03]Room temperature operation of Ge_1−xSn_x/Ge_1−x−ySi_xSn_y resonant tunneling diode

〇Shota Torimoto¹, Shuto Ishimoto¹, Yoshiki Kato¹, Mitsuo Sakashita¹, Masashi Kurosawa¹, Osamu Nakatsuka^1,2, Shigehisa Shibayama¹ (1. Grad. Sch. of Eng., Nagoya Univ. (Japan), 2. IMaSS, Nagoya Univ. (Japan))

11:45 AM - 12:00 PM JST(2:45 AM - 3:00 AM UTC)

[A-6-04]Agile Prototyping of AI Hardware LSIs Using Multi-Layer Aluminum Interconnects in a Minimal Fab Environment

〇Hirofumi Sumi¹, Hideharu Amano¹, Naonobu Shimamoto¹, Atsutake Kosuge¹, Yukinori Ochiai¹, Tohru Mogami¹, Yoshio Mita¹, Makoto Ikeda¹ (1. The University of Tokyo (Japan))