[A-6] Integration Technology on Si Wafer

11:45 AM - 12:00 PM JST(2:45 AM - 3:00 AM UTC)

[A-6-04] Agile Prototyping of AI Hardware LSIs Using Multi-Layer Aluminum Interconnects in a Minimal Fab Environment

〇Hirofumi Sumi¹, Hideharu Amano¹, Naonobu Shimamoto¹, Atsutake Kosuge¹, Yukinori Ochiai¹, Tohru Mogami¹, Yoshio Mita¹, Makoto Ikeda¹ (1. The University of Tokyo (Japan))