[A-7] 2D Material Integration

2:00 PM - 2:15 PM JST(5:00 AM - 5:15 AM UTC)

[A-7-02] Monolithic 3D CMOS Logic Integration of p-FinFET and 2D n-WSe₂ FET with Planar Local Back-Gate

〇Chi-Chun Cheng¹, Wen-Yuan Fei¹, Ching-Min Hsu¹, Po-Wen Chiu¹ (1. The Univ. of Hsinchu (Taiwan))

DOI:

https://doi.org/10.7567/SSDM.2025.A-7-02

Password required to view