[A-8] Vertical FET and New Devices

3:45 PM - 4:00 PM JST(6:45 AM - 7:00 AM UTC)

[A-8-03] Trimmable Via Pin Array Capacitor in Fully Compatible CMOS Logic Process in 16nm FinFET Platform

〇Wei-Hwa Lin¹, Jian-Yu Wang¹, Yue-Der Chih², Yih Wang², Jonathan Chang², Ya-Chin King¹, Chrong Jung Lin¹ (1. Inst. of Electronics Engineering, National Tsing Hua Univ. (Taiwan), 2. Design Technology Platform, Taiwan Semiconductor Manufac. Company (Taiwan))