Session Details

[A-8]Vertical FET and New Devices

Thu. Sep 18, 2025 3:15 PM - 4:15 PM JST
Thu. Sep 18, 2025 6:15 AM - 7:15 AM UTC
Room A (301, 3rd Floor)
Session Chair: Hiroyuki Ogawa (Rapidus Corp.), Takashi Matsukawa (AIST)

[A-8-01]Performance Enhancement Strategies in Vertical FETs for Next-Generation Logics

〇Zhihao Wang1, Ziqiao Xu1, Yu Liu1, Yanbang Chu1, Chuan Lan1, Yimeng Wang1, Runsheng Wang1, Ming Li1, Heng Wu1 (1. Peking University (China))

[A-8-02]Exploration and Insights into Vertical Nanowire/sheet FETs for Ultimate Scaled Circuits/Systems

〇Anabela Veloso1, Bjorn Vermeersch1, Abderrahim Tahiat2, Philippe Matagne1, Adrian Chasin1, Barry OSullivan1, Ruben Asanovski1, Bogdan Cretu2, Eddy Simoen3, Roger Loo1,3, Jeroen Scheerder1, Claudia Fleischmann1,4 (1. Imec (Belgium), 2. Normandy Univ., ENSICAEN, UNICAEN, CNRS, GREYC (France), 3. Ghent Univ. (Belgium), 4. KU Leuven (Belgium))

[A-8-03]Trimmable Via Pin Array Capacitor in Fully Compatible CMOS Logic Process in 16nm FinFET Platform

〇Wei-Hwa Lin1, Jian-Yu Wang1, Yue-Der Chih2, Yih Wang2, Jonathan Chang2, Ya-Chin King1, Chrong Jung Lin1 (1. Inst. of Electronics Engineering, National Tsing Hua Univ. (Taiwan), 2. Design Technology Platform, Taiwan Semiconductor Manufac. Company (Taiwan))

[A-8-04]Demonstration of Field Curvature Aberration Correction Using Concave Curved Color CMOS Image Sensors

〇Masahide Goto1, Shigeyuki Imura1, Hiroto Sato1 (1. NHK Sci. & Tech. Res. Labs. (Japan))