[B-1] 3D NAND Flash Memory

2:00 PM - 2:15 PM JST(5:00 AM - 5:15 AM UTC)

[B-1-02] Area Selective Deposited SiN for Confined Charge Trap Layer in 3D NAND Devices

〇Sana Rachidi¹, Laurent Breuil¹, Silvia Armini¹, Yoshitomo Hashimoto², Daigo Yamaguchi², Kimihiko Nakatani², Jie Li¹, Marta Coelho Silva¹, Geert Van den Bosch¹, Maarten Rosmeulen^1,3 (1. imec (Belgium), 2. KOKUSAI ELECTRIC CORPORATION (Japan), 3. KU Leuven (Belgium))