[C-2] Device Circuit Co-Design

3:45 PM - 4:00 PM JST(6:45 AM - 7:00 AM UTC)

[C-2-02] Measurement Circuit and Block Level Analysis of Continuous-Diffusion Structure induced Leakage Current in 5nm FinFET Process

〇Yuuki Uchida¹, Mitsuhiko Igarashi¹, Keiichiro Iwamoto¹, Yoshio Takazawa¹, Yasumasa Tsukamoto¹ (1. Renesas Electronics Corp. (Japan))