[C-2] Device Circuit Co-Design | 2025 International Conference on Solid State Devices and Materials

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Session Details

Oral Presentation12: Advanced and Innovative Circuits / Systems Interacting with Devices and Materials

[C-2]Device Circuit Co-Design

Tue. Sep 16, 2025 3:30 PM - 4:45 PM JST
Tue. Sep 16, 2025 6:30 AM - 7:45 AM UTC

Room C (303, 3rd Floor)

Session Chair: Yasuhiro Ogasahara (AIST), Mahfuzul Islam (Science Tokyo)

3:30 PM - 3:45 PM JST(6:30 AM - 6:45 AM UTC)

[C-2-01]Normally-Off CPU with Crystal Indium Oxide Enabling Power Gating Operation with Power Supply Voltage of 0.8 V

〇Masashi Fujita¹, Kouhei Toyotaka¹, Kazuaki Ohshima¹, Kazuma Furutani¹, Takehisa Sato¹, Haruki Katagiri¹, Yoshinori Ando¹, Motomu Kurata¹, Tsutomu Murakawa¹, Takanori Matsuzaki¹, Tatsuya Onuki¹, Yuto Yakubo¹, Shunpei Yamazaki¹ (1. Semiconductor Energy Laboratory Co., Ltd. (Japan))

3:45 PM - 4:00 PM JST(6:45 AM - 7:00 AM UTC)

[C-2-02]Measurement Circuit and Block Level Analysis of Continuous-Diffusion Structure induced Leakage Current in 5nm FinFET Process

〇Yuuki Uchida¹, Mitsuhiko Igarashi¹, Keiichiro Iwamoto¹, Yoshio Takazawa¹, Yasumasa Tsukamoto¹ (1. Renesas Electronics Corp. (Japan))

4:00 PM - 4:15 PM JST(7:00 AM - 7:15 AM UTC)

[C-2-03]Experimental Demonstration of 1FeFET-1RRAM Field Programmable Analog Modules

〇Zhengyang Lu¹, Xueyang Li¹, Zhetao Ding¹, Jiabao Ye¹, Chengji Jing², Xiao Yu², Peng Lin¹, Bing Chen², Yong Ding¹, Genquan Han², Ran Cheng¹ (1. Zhejiang Univ. (China), 2. Xidian Univ. (China))

4:15 PM - 4:30 PM JST(7:15 AM - 7:30 AM UTC)

[C-2-04]How Defect Dynamics in a pFET Can Be Interpreted as a Single-Node Reservoir Computer With Virtual Nodes

〇Yuanyang Guo^1,2, Robin Degraeve¹, Pablo Saraza-Canflanca¹, Erik Bury¹, Ingrid Verbauwhede² (1. imec (Belgium), 2. KU Leuven Univ. (Belgium))

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