[J-1] 3D Integration

2:00 PM - 2:15 PM JST(5:00 AM - 5:15 AM UTC)

[J-1-02] Evaluation of 19 nm-Half-Pitch Patterning by Nanoimprint Lithography Through Electrical Test of W-Damascene Interconnects Using Atomic-Scale Dry -Etching and Deposition Process

〇Kenta Suzuki¹, Tetsuya Ueda¹, Yuji Kasashima¹, Wataru Mizubayashi¹, Naoya Okada¹, Hiroyuki Ota¹, Masanaga Fukasawa¹, Yoshihiro Hayashi¹, Masaki Ishida², Tomomi Funayoshi², Hiromi Hiura², Masayuki Kagawa², Noriyasu Hasegawa², Kiyohito Yamamoto² (1. AIST (Japan), 2. Canon Inc. (Japan))