Session Details
[J-1]3D Integration
Tue. Sep 16, 2025 1:30 PM - 3:00 PM JST
Tue. Sep 16, 2025 4:30 AM - 6:00 AM UTC
Tue. Sep 16, 2025 4:30 AM - 6:00 AM UTC
Room J (411+412, 4th Floor)
Session Chair: Takashi Matsumoto (Tokyo Electron Technology Solutions Ltd.), Mayumi B. Takeyama (Kitami Inst. of Tech.)
[J-1-01 (Invited)]COW Integration Technology for Capacitor Embedded 3D Functional Interposer
〇Tatsuya Funaki1,2, Takayuki Ohba1 (1. Inst. of Sci. Tokyo (Japan), 2. Murata Manufac. Co., Ltd (Japan))
[J-1-02]Evaluation of 19 nm-Half-Pitch Patterning by Nanoimprint Lithography Through Electrical Test of W-Damascene Interconnects Using Atomic-Scale Dry -Etching and Deposition Process
〇Kenta Suzuki1, Tetsuya Ueda1, Yuji Kasashima1, Wataru Mizubayashi1, Naoya Okada1, Hiroyuki Ota1, Masanaga Fukasawa1, Yoshihiro Hayashi1, Masaki Ishida2, Tomomi Funayoshi2, Hiromi Hiura2, Masayuki Kagawa2, Noriyasu Hasegawa2, Kiyohito Yamamoto2 (1. AIST (Japan), 2. Canon Inc. (Japan))
[J-1-03]Die-level 3D integration with Via-last TSV from Multi-Project Wafers Towards Universal Access to 3D-ICs
〇Akihiro Tominaga1, Jiayi Shen2, Tetsu Tanaka1,2, Takafumi Fukushima1,2 (1. Graduate School of Engineering, Tohoku Univ. (Japan), 2. Graduate School of Biomedical Engineering, Tohoku Univ. (Japan))
[J-1-04]Void-Free, Low-temperature Direct Bonding of Si–Si for μLHP Integration in 3D ICs
〇Dianping Jiang1, Marie Sano2, Fumihiro Inoue2, Masaaki Hashimoto1, Hosei Nagano3, Munehiro Tada1 (1. Keio Univ. (Japan), 2. Yokohama National Univ. (Japan), 3. Nagoya Univ. (Japan))
[J-1-05]Etch development of Through-Dielectric-Via for Wafer Reconstruction with Gap-Fill Oxide
〇Quyang LIN1, Eoin Jackman1, Prathamesh Dhakras1, Jeongsoo Kim1, Violeta Georgieva1, Ye Lin1, Katia Devriendt1, Gerald Beyer1, Eric Beyne1 (1. IMEC (Belgium))