[J-1] 3D Integration

2:15 PM - 2:30 PM JST(5:15 AM - 5:30 AM UTC)

[J-1-03] Die-level 3D integration with Via-last TSV from Multi-Project Wafers Towards Universal Access to 3D-ICs

〇Akihiro Tominaga¹, Jiayi Shen², Tetsu Tanaka^1,2, Takafumi Fukushima^1,2 (1. Graduate School of Engineering, Tohoku Univ. (Japan), 2. Graduate School of Biomedical Engineering, Tohoku Univ. (Japan))