[J-1] 3D Integration

2:45 PM - 3:00 PM JST(5:45 AM - 6:00 AM UTC)

[J-1-05] Etch development of Through-Dielectric-Via for Wafer Reconstruction with Gap-Fill Oxide

〇Quyang LIN¹, Eoin Jackman¹, Prathamesh Dhakras¹, Jeongsoo Kim¹, Violeta Georgieva¹, Ye Lin¹, Katia Devriendt¹, Gerald Beyer¹, Eric Beyne¹ (1. IMEC (Belgium))