[K-5] Device II

9:30 AM - 9:45 AM JST(12:30 AM - 12:45 AM UTC)

[K-5-02] Threshold Voltage Tuning of Dual-gate MoS₂ Transistors Via Engineering of Dielectric Interfacial Layers

〇Xiangyu Wu¹, Zaoyang Lin^1,2, Pawan Kumar¹, Daire Cott¹, Marco Introna^1,2, Fengben Xi¹, Tien Dat Ngo¹, Sreetama Banerjee¹, Kaustuv Banerjee¹, Dennis Lin¹, Pierre Morin¹, Cesar Javier Lockhart de la Rosa¹, Gouri Sankar Kar¹ (1. IMEC (Belgium), 2. KU Leuven (Belgium))