[K-5] Device II | 2025 International Conference on Solid State Devices and Materials

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Session Details

Oral Presentation08: Low Dimensional Devices and Materials

[K-5]Device II

Thu. Sep 18, 2025 9:00 AM - 10:15 AM JST
Thu. Sep 18, 2025 12:00 AM - 1:15 AM UTC

Room K (413, 4th Floor)

Session Chair: Shu Nakaharai (Tokyo Univ. of Tech.), Takamasa Kawanago (AIST)

9:00 AM - 9:30 AM JST(12:00 AM - 12:30 AM UTC)

[K-5-01 (Invited)]Scalable 2D Memristors Heterointegration for Energy-Efficient Compute-in-Memory Hardware

〇Kah-Wee ANG¹ (1. National Univ. of Singapore (Singapore))

9:30 AM - 9:45 AM JST(12:30 AM - 12:45 AM UTC)

[K-5-02]Threshold Voltage Tuning of Dual-gate MoS₂ Transistors Via Engineering of Dielectric Interfacial Layers

〇Xiangyu Wu¹, Zaoyang Lin^1,2, Pawan Kumar¹, Daire Cott¹, Marco Introna^1,2, Fengben Xi¹, Tien Dat Ngo¹, Sreetama Banerjee¹, Kaustuv Banerjee¹, Dennis Lin¹, Pierre Morin¹, Cesar Javier Lockhart de la Rosa¹, Gouri Sankar Kar¹ (1. IMEC (Belgium), 2. KU Leuven (Belgium))

9:45 AM - 10:00 AM JST(12:45 AM - 1:00 AM UTC)

[K-5-03]Enhanced Intermediate Polarization: A Platform for Neuromorphic and Logic-in-Memory Computing

〇Heng XIANG¹, Yi Tong¹, Kah-Wee Ang² (1. Suzhou Laboratory (China), 2. National University of Singapore (Singapore))

10:00 AM - 10:15 AM JST(1:00 AM - 1:15 AM UTC)

[K-5-04]Reconfigurable 2D Ferroelectric PN Junctions for Integrated Synaptic-Neuronal Functions

〇Tianjiao Zhang¹, MaoXin Tian¹, Yang Xu¹, Bin Yu¹, Yuda Zhao¹ (1. Zhejiang University (China))