[SO-PS-02] 02: Advanced and Emerging Memories / New Applications

1:48 PM - 1:50 PM JST(4:48 AM - 4:50 AM UTC)

[SO-PS-02-10] Duration of Disturbance Tolerance Governed Bias Selection in 1T-DRAM Array

〇Abhinav Kranti¹, Rohit Kumar Nirala¹, Manish Gupta² (1. Indian Institute of Technology Indore (India), 2. Birla Institute of Technology and Science Pilani, K.K. Birla Goa Campus (India))