Session Details

[A-5]CFET Technology and Self-heating

Thu. Sep 18, 2025 9:00 AM - 10:30 AM JST
Thu. Sep 18, 2025 12:00 AM - 1:30 AM UTC
Room A (301, 3rd Floor)
Session Chair: Kuniyuki Kakushima (Science Tokyo), Satofumi Souma (Kobe Univ.)

[A-5-01 (Invited)]Challenges and Opportunities in CFET-Based SRAM Design

Yu-Cheng Lu1, Meng-Lin Wu1, Amit Ranjan Trivedi2, 〇Vita Pi-Ho Hu1 (1. National Taiwan Univ. (Taiwan), 2. Univ. of Illinois at Chicago (United States of America))

[A-5-02]A Simulation Study of Single Event Upset in Nanosheet-based CFET SRAM

〇Vanness Filbert Cierra1, Sida Wang1, Yoshinari Kamakura1 (1. Osaka Institute of Technology (Japan))

[A-5-03]Stacked Transistors with Nanosheet-based Flip FET for A10 Node: A DTCO Viewpoint

〇Haoran Lu1, Jingru Jiang1, Jiacheng Sun1, Ming Li1, Runsheng Wang1, Heng Wu1 (1. Peking Univ. (China))

[A-5-04]Alleviating Self-Heating-Effect in DFF by Introducing Equivalent Circuit in Double-Cell-Height CFET Design

〇Liang-Chi Huang1, Huei-Lin Shih1, Xiang-Ting Huang1, Pen-Yi Chu1, Bo-Hsun Juan1, Ko-Cheng Lu1, Tzu-Hsuan Chang1 (1. National Taiwan Univ. (Taiwan))

[A-5-05]Effect of an Additional Top Silicon Substrate on Mitigating
Self-Heating Effect in Complementary FET (CFET)

〇Seung Kyu Kim1,2, Johyeon Kim1, Kee-Won Kwon1, Jongwook Jeon1 (1. Sungkyunkwan Univ. (Korea), 2. Samsung Electronics Corp. (Korea))