2025 International Conference on Solid State Devices and Materials
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Session Details

Oral Presentation02: Advanced and Emerging Memories / New Applications

[B-2]In-Memory and Unconventional Computing 1

Tue. Sep 16, 2025 3:30 PM - 5:00 PM JST
Tue. Sep 16, 2025 6:30 AM - 8:00 AM UTC
Room B (302, 3rd Floor)
Session Chair: Ken Takeuchi (The Univ. of Tokyo), Xu Bai (NanoBridge Semiconductor, Inc.)
3:30 PM - 4:00 PM JST(6:30 AM - 7:00 AM UTC)

[B-2-01 (Invited)]Emerging Trends in MTJ-Based Nonvolatile Logic LSI Technology

〇Masanori Natsui1, Takahiro Hanyu1 (1. Tohoku Univ. (Japan))
4:00 PM - 4:15 PM JST(7:00 AM - 7:15 AM UTC)

[B-2-02]Approximate Euclidean Distance Computing Accelerator using Asymmetric Encoding Scheme in 3D-NAND Flash for High Performance Large Vector Database Search

〇Po-Hao Tseng1, Wei-Chen Lin1, Yu-Hsuan Lin1, Feng-Ming Lee1, Yu-Yu Lin1, Ming-Hsiu Lee1, Kuang-Yeu Hsieh1, Keh-Chung Wang1, Chih-Yuan Lu1 (1. Macronix International Co., Ltd. (Taiwan))
4:15 PM - 4:30 PM JST(7:15 AM - 7:30 AM UTC)

[B-2-03]Physical Modeling of Oxide-Semiconductor-Channel FeFETs for Content Addressable Memory Circuit Simulation

〇Xuebin Wang1, Fei Mo1,2, Zhuo Li4, Guanhua Yang3, Masaharu Kobayashi4, Yeliang Wang1 (1. Beijing Inst of Tech. (China), 2. Beijing Inst of Tech.(Zhuhai) (China), 3. The Inst of Microelectronics of the Chinese Academy of Sci. (China), 4. The Univ. of Tokyo (Japan))
4:30 PM - 4:45 PM JST(7:30 AM - 7:45 AM UTC)

[B-2-04]Column-wise Weight Value Inversion (Colwin)of ReRAM CiM to Reduce MAC Error during Data-retention

〇Yusuke Izume1, Yusuke Hirata1, Naoko Misawa1, Masahiro Morimoto2, Takeshi Ohara2, Chihiro Matsui1, Ken Takeuchi1 (1. The University of Tokyo (Japan), 2. Nuvoton Technology Corporation Japan (Japan))
4:45 PM - 5:00 PM JST(7:45 AM - 8:00 AM UTC)

[B-2-05]Fine-Grained Extraction Method of Discrete Shift and Spike RTN in 40nm TaOX-based Analog ReRAM for CiM Applications

〇Yushi Abarra1, Naoko Misawa1, Chihiro Matsui1, Ken Takeuchi1,2 (1. Department of Electrical Eng. and Info. Systems, The Univ. of Tokyo (Japan), 2. Systems Design Lab., Graduate School of Eng., The Univ. of Tokyo (Japan))
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