Session Details

[J-5]In-Memory and Unconventional Computing 2

Thu. Sep 18, 2025 9:00 AM - 10:15 AM JST
Thu. Sep 18, 2025 12:00 AM - 1:15 AM UTC
Room J (411+412, 4th Floor)
Session Chair: Kazuyuki Kouno (Nuvoton Technology Corp. Japan), Yumeng Zheng (Tokyo Univ. of Science)

[J-5-01]Fluorine Surface Engineering for Vt Control and Memory Window Boost in HZO FeFET toward High-Performance Analog In-Memory Computing.

〇Kyungsoo Park1, Sangkuk Han1, Chulwon Chung1, MinHyuk Kim1, Changhwan Choi1,2 (1. Division of Materials Science and Engineering, Univ. of Hanyang (Korea), 2. Department of Semiconductor Engineering, Univ. of Hanyang (Korea))

[J-5-02]Comparative Scaling Analysis of Charge-Trap TFET (CT-TFETs) and Charge-Trap MOSFETs (CT-MOSFETs) for Reliable Neuromorphic Synapse Arrays

〇Jae Seung Woo1,2, Woo Young Choi1,2 (1. Seoul National University (Korea), 2. The Inter-university Semiconductor University Research Center (ISRC) (Korea))

[J-5-03]Tiny & Error-robust Edge ViT CiM with 1/10 Training Parameters by Iteratively Error Injected LoRA (Ei-LoRA)

〇Naoko Misawa1, Ruiqi Zhang1, Tao Wang1, Chihiro Matsui1, Ken Takeuchi1 (1. The University of Tokyo (Japan))

[J-5-04]Quantized Neuron-Implementable Ternary-State Vertical NAND Flash Memory for the Highly Reliable Neuromorphic Computing

〇Jin Ho Chang1, Jae Seung Woo1, Jae Hyun Nam1, Da Eun Yang1, Kyungmoon Kim1, Woo Young Choi1 (1. Seoul National University (Korea))

[J-5-05]A Heterogeneous-Integrated Computing-in-Memory Neuromorphic Architecture Based on Multi-Level IGZTO with 34.8 TOPS/W High-Power-Efficiency

〇He Zhaolong1,4, Chen Kai2,4, Wang Hanfeng2,4, Guo Yaolei2,4, Cheng Yue2,4, Tang Chenhao2,4, Li Yunlong2,4, Zhang Rui2, Li Junkang2,3,4, Ma Yitao2,3,4 (1. University of Science and Technology of China (China), 2. Zhejiang University (China), 3. ZJU-Hangzhou Global Scientific and Technological Innovation Center (China), 4. Zhejiang ICsprout Semiconductor Co., Ltd. (China))