2026 International Conference on Solid State Devices and Materials
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Session Details

Oral Presentation01: Advanced CMOS: Material Science / Process Engineering / Device Technology

[A-4]New device architecture

Wed. Sep 16, 2026 10:30 AM - 12:00 PM JST
Wed. Sep 16, 2026 1:30 AM - 3:00 AM UTC
Room A(Convention Hall 1, 2rd Floor)
Session Chair:Anabela Veloso(imec), Pin Su(National Yang Ming Chiao Tung Univ.)
10:30 AM - 11:00 AM JST(1:30 AM - 2:00 AM UTC)

[A-4-01 (Invited)]Value Proposition of Vertical Transistor for Future’s Logic Applications: Symmetry, Drivability and Routability

〇Yanbang Chu1, Yu Liu1, Ziqiao Xu1, Runsheng Wang1, Ming Li1, Heng Wu1 (1. School of Integrated Circuits, Peking University (China))
11:00 AM - 11:15 AM JST(2:00 AM - 2:15 AM UTC)

[A-4-02]Critical PPA Examination of SRAMs with VFET Evolutions: From Frontside to Dual-sided and Stacking

〇Xinyue He1, Siyuan Liu1, Yuji Cheng1, Yu Liu1, Xiangyu Yan1, Runsheng Wang1, Ming Li1, Xing Zhang1, Heng Wu1 (1. School of Integrated Circuits, Peking University (China))
11:15 AM - 11:30 AM JST(2:15 AM - 2:30 AM UTC)

[A-4-03]PPA Examination of Flip Vertical FET (FVFET), a Novel Stacked VFET Architecture

〇Jiahao Zhang1, Ziqiao Xu1, Siyuan Liu1, Yanbang Chu1, Xinyue He1, Yu Liu1, Runsheng Wang1, Ming Li1, Heng Wu1 (1. School of Integrated Circuits, Peking Univ. (China))
11:30 AM - 11:45 AM JST(2:30 AM - 2:45 AM UTC)

[A-4-04]Short-Term Synaptic Plasticity Emulation without Impact Ionization Using a Dual-Gate PN-Body Tied SOI-FET

〇Yukihiko Yamazaki1, Haruki Yonezaki1,2, Jiro Ida1, Takayuki Mori1 (1. Kanazawa Inst. of Tech. (Japan), 2. KIOXIA Corp. (Japan))
11:45 AM - 12:00 PM JST(2:45 AM - 3:00 AM UTC)

[A-4-05]Monolithic 3D All-WSe2 CFET Inverter Enabled by Localized Electron-Beam Band Engineering and 2D-Compatible Process Engineering

〇Chi-Chun Cheng1, Chun-Yen Hsiao1, Long-An Lee1, Nguyen Huynh-Uyen-Phuong1, Po-Wen Chiu1 (1. National Tsing Hua University (Taiwan))
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