Si/Ge core-shell nanowire (NW) structures have recently attracted great attention for high electron mobility transistors. A notable advantage of these heteroarchitectures lies in their ability to enhance hole gas accumulation. The Ge shell acts as an efficient conductor for charge carriers, enabling the accumulation of holes within the transistor's channel region. The enhanced accumulation produces superior electrical characteristics, including heightened carrier mobility and conductivity, ultimately leading to substantial improvements in transistor functionality. In this study, SiNWs formed by vapor-liquid-solid (VLS) growth using Al catalysts were applied for Si/Ge core-shell heterostructures. The focus is on targeting vertical-aligned SiNWs with smooth surfaces and single crystalline properties, while also addressing the issue of metal catalyst contamination. Al-catalyzed SiNW formation, p-Si intermediate layer, and p-Si shell outermost layer in various designs of SiNW/i-Ge, SiNW/p-Si/i-Ge, and SiNW/i-Ge/p-Si core-shell structures were optimized for maximize hole gas generation in Ge channel layer.