[Mo-P] Power Devices | ICSCRM2026

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Session Details

Poster SessionTrack 07 Power Devices

[Mo-P]Power Devices

Mon. Sep 28, 2026 1:00 PM - 3:00 PM JST
Mon. Sep 28, 2026 4:00 AM - 6:00 AM UTC

Poster-B(4th Floor, G401+G402)

[Mo-P-49]Structural Origin of Inversion Layer Formation via Stacking-Fault-Mediated Hole Transport in 3C/4H-SiC MOS Structures

*Kota Gejo¹, Tetsuo Hatakeyama¹, Hiroyuki Nagasawa² (1. Univ. of Toyama Pref (Japan), 2. Cusic Inc (Japan))

[Mo-P-50]Analytical Method for Parameter Extraction From Hall Measurement Data in Aluminum Implanted SiC Test Structures

*Edmund K Banghart¹, Daniel J Lichtenwalner¹, Hemant Dixit¹, Sei-Hyung Ryu¹ (1. Wolfspeed (USA))

[Mo-P-51]Dual-Path Current in Accumulation-Type SiC MOSFETs

*AMJED ALI^1,2, Daniel Haasmann, Philip Tanner, Jordan Nicholls, Sima Dimitrijev (1. School of Engineering and Built Environment, Griffith University, Nathan, Qld (Australia), 2. Queensland Quantum and Advanced Technologies Research Institute, Griffith University, Nathan, Qld (Australia))

[Mo-P-52]Measurement of Temperature-Dependent Large-Signal Hysteresis in Output Capacitance of SiC MOSFETs

*Taiki Nishioka¹, Hajime Takayama¹, Kazutaka Kanegae¹, Hiroyuki Nishinaka¹, Michihiro Shintani¹ (1. Kyoto Inst. of Tech. (Japan))

[Mo-P-53]Curve Tracer Approach for Accurate Characterization of Output Characteristics of SiC MOSFETs in 1^st and 3^rd Quadrant

Maximilian Paul Goller¹, *Mohamed Alaluss¹, Madhu Lakshman Mysore¹, Gengqi Li¹, Dezhi Yang¹, Josef Lutz¹, Thomas Basler¹ (1. Chemnitz University of Technology (Germany))

[Mo-P-54]Impact of P+ Body Layout on Capacitance and Third Quadrant Characteristics of Tri-Gate SiC MOSFETs

Pei-Chi Liao¹, *Kung-Yen Lee^1,2, Pei-Chun Liao¹, Ruei-Ci Wu², Yu-Ying Li¹, Yung-Mei Lin¹ (1. National Taiwan University (Taiwan), 2. SiCEV Electronics Co., Hsinchu (Taiwan))

[Mo-P-55]Variation of Dynamic Characteristics in SiC MOSFETs induced by Edge Termination Topology

*PEI-CHUN LIAO¹, KUNG-YEN LEE^1,2, YAN-YU WEN¹, PEI-CHI LIAO¹, TIEN-CHIN SHIH², RUEI-CI WU³ (1. Graduate School of Advanced Technology, National Taiwan Univ. (Taiwan), 2. Department of Engineering Science and Ocean Engineering, National Taiwan Univ. (Taiwan), 3. SiCEV Electronics Co., Ltd., Taiwan (Taiwan))

[Mo-P-56]Dynamic C-V Characterization of Commercial SiC Power MOSFETs

*Tibet Alpay¹, Michel Nagel¹, Ivana Kovacevic-Badstuebner¹, Ulrike Grossner¹ (1. APS - ETH Zurich (Switzerland))

[Mo-P-57]Miller Capacitance Characterization of SiC Power MOSFETs Beyond Datasheets

*Michel Nagel¹, Ivana Kovacevic-Badstuebner¹, Ulrike Grossner¹ (1. APS - ETH Zurich (Switzerland))

[Mo-P-58]3D vs. 2D TCAD: The Right Choice for Simulating 4H-SiC MOSFETs?

*Hemant Dixit¹, Jae Park¹, Jeff Joohyung Kim¹, Sei-Hyung Ryu¹ (1. Wolfspeed (USA))

[Mo-P-59]Physics-based Compact Model of SiC Power MOSFET for Process Corner Analysis

*Arman Ur Rashid¹, Jeff Joohyung Kim¹, Edmund Banghart¹, Sei-Hyung Ryu¹ (1. Wolfspeed, Inc. (USA))

[Mo-P-60]Robust and Universal SPICE Model Structure for Variable Capacitance with Negative-Feedback Configuration

*Yuichiro Nanen¹ (1. ROHM co. Ltd. (Japan))

[Mo-P-61]A Modified Coupled Charge-driven Reverse Recovery SPICE Model for Describing the Dynamic Behavior of SiC MOSFETs’ Intrinsic Body Diode

*Ting-Fu Chang¹, Fu-Jen Hsu^1,2, Hsiang-Ting Hung¹, Chung-Ju Yu¹, Cheng-Tyng Yen¹, Chih-Fang Huang² (1. Fast SiC Semiconductor Inc. (Taiwan), 2. National Tsing Hua University (Taiwan))

Late News

[Mo-P-88LN]Simulation of Reverse Recovery Characteristics in SiC PiN Diodes with a Carrier-Trapping Layer Formed in the Anode Region

*Satoshi Asada¹, Koich Murata¹, Hidekazu Tsuchida¹ (1. Central Research Institute of Electric Power Industry (Japan))