Session Details
[Tu-P]MOS Gate Stack Processing and Characterization
Tue. Sep 29, 2026 4:00 PM - 6:00 PM JST
Tue. Sep 29, 2026 7:00 AM - 9:00 AM UTC
Tue. Sep 29, 2026 7:00 AM - 9:00 AM UTC
Poster-C(4th Floor, G403+G404)
[Tu-P-62]Interface Engineered ALD SiO2 / SiC MOS oxide stack using PEALD-enabled controlled nitridation
*Andrii Voznyi1, Tatiana Ivanova1, Mikko Söderlund1, Patrick Rabinzohn1, Tamara Fidler2, Patrick Schmid2, Alexander Schmid3, Franziska Beyer3 (1. Beneq Oy (Finland), 2. Centrotherm International AG (Germany), 3. Fraunhofer IISB (Germany))
[Tu-P-63]Enhanced electrical characteristics of 4H-SiC MOSFETs with atomic layer deposited SiO2 gate dielectrics via ultrathin interfacial passivation
*Bongmook Lee1, Veena Misra2 (1. SUNY Polytechnic Institute (USA), 2. North Carolina State Univesity (USA))
[Tu-P-64]Process Optimization of SiO2/AlON Gate Stack for Reliable 4H-SiC MOS-Channel Devices
*Pengwei Zhou1, Heng Wang1, Yangming Du1, Yingchen Yang1, Kevin Jing CHEN1 (1. The Hong Kong University of Science and Technology (Hong Kong))
[Tu-P-65]Impact of Atomic Layer Etching Surface Pretreatment on ALD
SiO2/4H-SiC MOS Interface and Channel Transport Properties
*Mustafa Akif YILDIRIM1, Vishal Ajit Shah1, Sean Cho2, Katarzyna Stokeley2, Harriet van der Vliet2, Sami Bolat3, Peter M Gammon1, Marina Antoniou1, Arne Benjamin Renz1 (1. Univ. of Warwick (UK), 2. Oxford Instruments Plasma Tech. (UK), 3. Hitachi Energy Semiconductors Switzerland Ltd (Switzerland))
[Tu-P-66]Impact of nitrogen-based pre-ALD treatments and post-deposition
annealing on SiO2/4H-SiC and Al2O3/4H-SiC MOS capacitors
Emanuela Schilirò1, Raffaella Lo Nigro1, Marco Zignale1, Patrick Fiorenza1, Giuseppe Greco1, Valerio Votadoro1, Salvatore Di Franco1, Filippo Giannazzo1, Arpita Saha2, Yi Shu2, *Fabrizio Roccaforte1 (1. CNR-IMM, Catania (Italy), 2. Oxford Instruments Plasma Technology, Bristol (UK))
[Tu-P-67]Enhancing Performance of 4H-SiC CMOS Integrated Circuits via Atomic Layer Deposition Gate oxide
*Po-Han Wang1, I-Chen Tsai1, Cheng-Shu Chang1, Yun-Ting Huang1, Nai-Quan Sun1, Bing-Yue Tsui1 (1. National Yang Ming Chiao Tung University (Taiwan))
[Tu-P-68]Effects of Wet and Nitric Oxide Post-Deposition Annealing on the Interface Quality and Long-term Reliability of LPCVD SiO2 on 4H-SiC
*I-Chen Tsai1, Bing-Yue Tsui1, Shih-Lung Tsai2, Kuan-Wei Chu2, Tien-Min Yuan2 (1. National Yang Ming Chiao Tung Univ. (Taiwan), 2. Mosel Vitelic Inc. (Taiwan))
[Tu-P-69]Reducing Cover Wafer Effect in Dry Oxidation of 4H-SiC in Thermal Oxidation Furnace
*Tamara Fidler1, Silvan Schick1, Patrick Schmid1 (1. centrotherm international AG (Germany))
[Tu-P-95LN]TCAD Validation of C–V Interface-Trap Extraction in 4H-SiC MOS Capacitors Across Four Gate Oxide Processes
*Michael Mawby1, Philip Mawby1, David Mawby1, Arne Renz2, Miriam John2, Peter Gammon2 (1. KuasaSemi Ltd. (UK), 2. Warwick Univ. (UK))
[Tu-P-96LN]Interface Trap Density Estimation by Forward Modelling of Quasi-Static
and High Frequency C–V characteristics in 4H-SiC MOS Capacitors
*James Lobry1, Rhys Washer1, Jon Evans1, Owen Guy1, Saptarsi Ghosh1, Tim Mottram2, Mike Jennings1 (1. Swansea University (UK), 2. Siemens (UK))