[9p-N101-1~10] [Open Symposium] Cutting-edge logic semiconductors and associated technologies | The 86th JSAP Autumn Meeting 2025

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Symposium (Oral)Symposium : [Open Symposium] Cutting-edge logic semiconductors and associated technologies

[9p-N101-1~10][Open Symposium] Cutting-edge logic semiconductors and associated technologies

Tue. Sep 9, 2025 1:30 PM - 5:25 PM JST
Tue. Sep 9, 2025 4:30 AM - 8:25 AM UTC

N101 (Lecture Hall North)

1:30 PM - 1:35 PM JST(4:30 AM - 4:35 AM UTC)

[9p-N101-1]Opening

〇Osamu Nakatsuka¹ (1.Nagoya University)

1:35 PM - 2:05 PM JST(4:35 AM - 5:05 AM UTC)

[9p-N101-2]The Latest activities on GAA-NS-FET and 3DSFET (CFET) technologies

〇Hitoshi Wakabayashi¹ (1.Science Tokyo)

2:05 PM - 2:35 PM JST(5:05 AM - 5:35 AM UTC)

[9p-N101-3]Recent trends of gate stack technology

〇Shinji Migita^1,2 (1.AIST, 2.LSTC)

2:35 PM - 3:05 PM JST(5:35 AM - 6:05 AM UTC)

[9p-N101-4]Emerging Trends in Post-Cu BEOL and Future Perspectives on Backside Interconnect

〇Fumihiro Inoue¹ (1.Yokohama Nat. Univ.)

3:05 PM - 3:35 PM JST(6:05 AM - 6:35 AM UTC)

[9p-N101-5]Latest Trends in Epitaxial Growth and Silicon Substrates for Beyond 2nm Technology Node

〇Atsushi Ogura^1,2, Koji Usuda² (1.Sci.and Tech., Meiji Univ, 2.MREL, Meiji Univ.)

3:45 PM - 4:15 PM JST(6:45 AM - 7:15 AM UTC)

[9p-N101-6]AI technology to accelerate semiconductor manufacturing process development

〇Kentaro Kutsukake¹, Toru Ujihara¹, Shota Seki², Masaki Takaishi², Hiroki Nagakura³, Koichi Tanigawa³, Yuta Nagai⁴ (1.Nagoya Univ., 2.AIxtal, 3.Sony Semiconductor Manufacturing, 4.GlobalWafers Japan)

4:15 PM - 4:45 PM JST(7:15 AM - 7:45 AM UTC)

[9p-N101-7]HZO ferroelectric memory and its implications for novel computing technologies

〇Kasidit TOPRASERTPONG¹, Zhenhong Liu¹, Kosuke Ito¹, Xuanhedong Gao¹, Seong-Kun Cho¹, Zuocheng Cai¹, Eishin Nako¹, Shin-Yi Min¹, Rikuo Suzuki¹, Ryosho Nakane¹, Mitsuru Takenaka¹, Shinichi Takagi^1,2 (1.Univ. Tokyo, 2.Teikyo Univ.)

4:45 PM - 5:15 PM JST(7:45 AM - 8:15 AM UTC)

[9p-N101-8]Advanced Thermal Management Devices and Charavterization Method s for 3D Semiconductor Chips

〇Hosei Nagano¹ (1.Nagoya University)

5:15 PM - 5:20 PM JST(8:15 AM - 8:20 AM UTC)

[9p-N101-9]Closing 1

〇Takaaki Tsunomura¹ (1.Tokyo Electron Ltd.)

5:20 PM - 5:25 PM JST(8:20 AM - 8:25 AM UTC)

[9p-N101-10]Closing 2

〇Takeyasu Saito¹ (1.Osaka Metropolitan Univ.)

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